The present invention relates to integrated circuits, and in particular, to a bias circuit integrated on a silicon wafer.
A bias circuit is often used in integrated circuits to apply a reference voltage to current generators or to voltage generators. A bias circuit 10 is shown in FIG. 1, and includes first and second branches B1, B2. The first branch B1 comprises a PMOS transistor TP1 and an NMOS transistor TN1 connected in series. The second branch B2 comprises a PMOS transistor TP2, an NMOS transistor TN2 and a resistor R connected in series. The transistor TN2 has a gate width to length ratio (W/L ratio) that is equal to N times that of the transistor TN1. This is generally achieved by NMOS transistors identical to the transistor TN1, arranged in parallel.
The branches B1, B2 are supplied by a voltage Vcc applied to the sources of the PMOS transistors, and are arranged as a current mirror. The gate G of the transistor TP2 is, for example, connected to the gate of the transistor TP2, which is also connected to its drain D. To ensure the self-bias of the circuit 10 at a determined operating point, the gate of the transistor TN2 is connected to the gate of the transistor TN1, which is connected to its drain. Therefore, after being activated, the bias circuit 10 is set to an operating point so that an identical current I passes through the branches B1, B2. This current I is assumed to be constant.
The bias circuit 10 shown in FIG. 1 may also be a current generator. A reference voltage Vref that is representative of the current I passing through the branches B1, B2 is sampled at one point of the circuit 10, for example, on the gate of the transistor TN1, and is applied to the gate of an external NMOS transistor TN0 arranged in an external branch Be. The transistor TN0 is identical to the transistor TN1, and provides a current Ie equal to the current I in the external branch Be. The transistor TN0 is therefore equivalent to a current generator inserted into the branch Be. Other current generators can be created in this way by applying the voltage Vref to other branches of an integrated circuit.
This bias circuit 10 has the advantage of being very simple, and small in size in terms of the silicon surface occupied. However, it is sensitive to variations in the supply voltage Vcc or in the temperature. For a better understanding, FIG. 2 shows curves of the current/voltage of the bias circuit 10 as a function of the temperature T. The current I varies with the temperature for a given supply voltage Vcc. Furthermore, for a given temperature T, the current I rises when the voltage Vcc rises.
In view of the foregoing background, an object of the present invention is to overcome the above described voltage variation defects and temperature variation defects in a relatively straightforward manner without using complex stabilization circuits.
More particularly, an object of the present invention is to provide a bias circuit of the above-mentioned type that has a stable and constant current over a wide range of supply voltage values.
More particularly, another object of the present invention is to provide a bias circuit of the above-mentioned type that has a stable and constant current over a wide range of temperatures.
One of the objects of the present invention is achieved by providing a bias circuit integrated on a silicon wafer that includes a first branch and a second branch. The first branch comprises a first PMOS transistor in series with a first NMOS transistor. The second branch comprises a second PMOS transistor, a second NMOS transistor and a resistor all in series. The gate of the first NMOS transistor is connected to the gate of the second NMOS transistor. The first branch and the second branch are arranged as a current mirror. The bias circuit also includes a third branch comprising at least a third PMOS transistor in series with at least a third NMOS transistor. The third PMOS and NMOS transistors are arranged to maintain a voltage that is identical or roughly identical to the drain voltage of the first PMOS transistor and on the drain of the second PMOS transistor.
According to one embodiment, the gate of the third PMOS transistor is connected to the drain of the second PMOS transistor, and the gate of the third NMOS transistor is connected to the drain of the third NMOS transistor and to the gate of the first NMOS transistor. According to another embodiment, the drain of the first PMOS transistor is connected to the gate of the first PMOS transistor.
Another object of the present invention is achieved by providing a bias circuit of the type described above, in which the resistor has a temperature coefficient chosen so that the variations with the temperature ensure the stability of a current passing through the second branch.
According to one embodiment, the resistor comprises at least a first and a second resistor in series or in parallel. These resistors have distinct temperature coefficients. According to another embodiment, the first resistor is in N doped silicon and the second resistor is in N+ or P+ doped silicon.
According to one embodiment, the first branch comprises a fourth NMOS transistor arranged in series between the first PMOS transistor and the first NMOS transistor, and has a threshold voltage that is lower than that of the first NMOS transistor. The second branch comprises a fifth NMOS transistor arranged in series between the second PMOS transistor and the second NMOS transistor, and has a threshold voltage that is lower than that of the second NMOS transistor. The gates of the fourth and fifth NMOS transistors are connected to the gate of the first NMOS transistor.
According to another embodiment, the second NMOS transistor comprises a plurality of NMOS transistors in parallel. According to another embodiment, the bias circuit comprises an output delivering a reference voltage sampled on the gate of the first NMOS transistor. The output is connected to the gate of an external transistor arranged in an external branch.
According to one embodiment, the first and the second resistors have, at ambient temperature, values R10, R20, which meet the following equations: (1) R10=R0(xcex12xe2x88x92xcex1)/(xcex12xe2x88x92xcex11); and (2) R20 =R0(xcex1xe2x88x92xcex11)/(xcex12xe2x88x92xcex11). R0 is the value of the resistor at ambient temperature, xcex11 is the temperature coefficient of the first resistor, xcex12 is the temperature coefficient of the second resistor, and xcex10 is the temperature coefficient of the resistor ensuring the stability in temperature of the bias circuit.